A conventional memory device, such as an NAND flash memory, includes a plurality of memory cell transistors (hereinafter memory transistors) connected in series, and selects transistors disposed at both ends of the plurality of memory transistors connected in series to improve integration density. Since the memory transistor stores information based on the presence of storages of charge, it is configured such that a tunnel insulating layer, a charge storage layer, a blocking insulating layer and a gate electrode are stacked in order. In contrast, since there is no need for the select transistor to store charge, no tunnel insulating layer and no charge storage layer are required. Accordingly, the select transistor is configured such that a gate insulating layer and a gate electrode are stacked in order.
In this manner, the memory transistor is different in structure from the select transistor. Because of such a difference in structure, conventional manufacturing processes include separate processes for forming a memory transistor and a select transistor. Since the memory transistor forming process and the select transistor forming process are separately performed, the number of manufacturing processes for memory devices is increased, thereby increasing turn around time (TAT).
To avoid this problem, there has been proposed a memory device manufacturing method in which a select transistor is configured such that a tunnel insulating layer, a blocking insulating layer and a gate electrode are stacked in order and a structure of a memory transistor is substantially equal to that of the select transistor.
In this proposed method, silicon (Si) is contained in an aluminum oxide (Al2O3) layer used as a blocking insulating layer in order to suppress a variation of a flat band voltage (Vfb) which results from charge trap at an interface between the tunnel insulating layer and the blocking insulating layer of the select transistor. Since the silicon is contained in the Al2O3 layer, the amount (or density) of charges trapped at the interface between the tunnel insulating layer and the blocking insulating layer may be decreased to suppress shift (variation) of Vfb.
However, in the above proposed method, it is impossible to completely prevent such a variation of Vfb due to the charge trap although it may decrease the shift of Vfb. In addition, since the structure of the memory transistor is not completely equal to that of the select transistor, it requires an additional process of removing the charge storage layer from a region where the select transistor is formed after forming the tunnel insulating layer and the charge storage layer on a semiconductor substrate.